The modules are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one rank of 512Mx64 (4GB) and two ranks of 1024Mx64 (8GB) high-speed memory array. Modules use eight 512Mx8 (4GB) and sixteen 512Mx8 (8GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. Theuse of these common design files minimizes electrical variation between suppliers. The DIMM is intended for use in applications operating of 800MHz clock speeds and achieves high-speed data transfer rates of 12800Mbps. Prior to any access operation, the device CAS latency and burst/length/operation type must be programmed into the DIMM by address inputs and I/O inputs using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128bytes are available for use by the customer.
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